1. Field of the Invention
The present invention relates to a controller for a non-volatile semiconductor memory device.
2. Description of the Related Art
A NAND cell type flash memory has been conventionally known as a kind of non-volatile semiconductor memory device. Normally, the NAND cell type flash memory is provided with a plurality of blocks serving as a set of memory cells. In each of the blocks, a plurality of memory cells are arrayed. Specifically, in each of the blocks (e.g., 64 KB), the plurality of memory cells arrayed in one direction form a page (e.g., 1 KB) per which data is read, and further, a plurality of pages (e.g., 64) are arrayed in a direction perpendicular to the above-described direction. The memory cell to be read, written, erased, and the like is selected by a selecting transistor connected to a control circuit. The memory cell indicates “1” according to a threshold voltage level in an erasure state. In the meantime, in writing “0” in the memory cell, an electron is injected into a floating gate in the memory cell, thereby setting a threshold voltage level indicating “0”. Incidentally, in the NAND cell type flash memory, a threshold voltage can be transited from a low level (a level indicating “1”) to a high level (a level indicating “0”) during writing, but not vice versa. The memory cell need be erased in a unit of the above-described block in order to transit the threshold voltage from the high level to the low level.
Information amount which can be stored in each of the memory cells is not limited to 1 bit (i.e., binary data). For example, a 4-value NAND cell type flash memory can store 4-value data (i.e., information of 2 bits) on four threshold voltage levels. Here, in general, variations are generated in a device such as an oxide film constituting the memory cell. Therefore, threshold voltage levels held by a plurality of memory cells with respect to the threshold voltage level set during writing form a distribution. Read data in the memory cell is decided by comparing a threshold voltage level held by the memory cell with a decision threshold voltage level. As a consequence, a writing threshold voltage level corresponding to a data pattern is set so as to prevent any overlap of the distributions between the adjacent threshold voltage levels. The decision threshold voltage level is set such that the overlap of the distributions between the adjacent writing threshold voltage levels becomes minimum. However, as information amount which can be stored in the memory cell increases (multivalent), an interval between the writing threshold voltage levels for representing each of the pieces of information becomes narrower, thereby increasing a possibility of occurrence of the overlap of the distributions between the adjacent writing threshold voltage levels. In addition, when an electric charge leaks from the floating gate due to a secular change in the memory cell or the oxide film is fatigued due to repetitive writing, erasing, and the like, the distribution of the threshold voltage levels is varied. That is to say, even if a decision threshold voltage level is optimum at certain timing, it may not be optimum at another timing.
US 2008/0263266 discloses a reading method for a flash memory, in which decision threshold voltage levels are widely inched, to produce a histogram of a threshold voltage level held in each of the memory cells. In the reading method, one decision threshold voltage level capable of minimizing a reading error out of settable decision threshold voltage levels is estimated based on the histogram.
In contrast, it is becoming difficult for a NAND cell type flash memory to maintain reliability (error resistance) to an extent equal to that of an old generation caused by evolution of generation such as a multivalue or a process. As a consequence, an error correcting code (e.g., a Low Density Parity Check (LDPC) code) having a high error correction capability for soft decision decoding is desirable rather than an error correcting code (e.g., a BCH code) for hard decision decoding, like a non-volatile semiconductor memory system disclosed in JP-A 2008-16092 (KOKAI).
In order to perform the soft decision decoding, it is necessary to set more decision threshold voltage levels than those in the case where the hard decision decoding is performed. For example, when the hard decision decoding is performed in reading a 4-value NAND cell type flash memory, a decision may be made on four levels by decision threshold voltages on three stages. In contrast, when the soft decision decoding is performed in the 4-value NAND cell type flash memory, a decision need be made on 8 or 16 levels by decision threshold voltages on 7 or 15 stages.
Like the non-volatile semiconductor memory system disclosed in JP-A 2008-16092 (KOKAI), it is not sufficient from the viewpoint of minimization of a decoding error in the soft decision decoding to set the decision threshold voltage levels for the soft decision decoding in such a manner as to equally divide the decision threshold voltage level for the hard decision decoding.